There are many different markets and applications that require integration of ultra large resistors (>tens of Mega Ohms) in an area-efficient manner, while also achieving as low a variation as possible in the value of the resistance, without having to resort to trimming techniques. In an analog system, this requirement can be anywhere in the chip, either at the boundaries to the external world or deep inside. For simplicity and ease of understanding, an example of a single-ended to differential conversion architecture using a well-known instrumentation amplifier topology is used for illustration.
FIG. 1 shows a schematic block diagram (100) of a single-ended to differential conversion Instrumentation Amplifier architecture (105). As shown in this example, this system may comprise the first and second amplifiers (103 and its symmetrical counterpart at the bottom 103a). The input of the first amplifier (103) is AC coupled to a single-ended voltage VIN (112) through the large external capacitor CHPF (101), and the input of the second amplifier (103a) is coupled to an AC ground voltage. The first and second amplifiers (103 and 103a) are biased by a common-mode voltage VCM (104), through a resistor RHPF (102). The differential outputs VOUTP (106) and VOUTM (107) are generated through the symmetric feedback network comprising R1 (109,110) and R2 (108). The final output of this system is the differential voltage VOUT_DIFF (111), that is then sent out to the next stage in the signal chain for further processing. Such processing usually involves an Analog to Digital Conversion (ADC) operation.
There are several applications that require this kind of processing of the input signal VIN (112) for pre-amplification before being converted into the digital domain for further processing. The voltage gain at the differential output (111) is given by the expression
  G  =            (                                    V                          out              ⁢                                                          ⁢              p                                -                      V                          out              ⁢                                                          ⁢              m                                                V          in                    )        =          (              1        +                  2          ⁢                                    R              1                                      R              2                                          )      and can be conveniently set by adjusting the resistor ratio, as desired. The symmetrical nature of this solution makes it a highly preferred pre-amplification stage for several applications, requiring conversion of a single-ended input signal to a differential output.
A typical example of such a system is in an audio microphone input path, where the analog microphone signal is generated with respect to the headset jack ground. For the rest of this description, this microphone example will be used to illustrate embodiments of the invention, so that the concept is clear. However, the exact same arguments/considerations are applicable in other low frequency systems as well, such as medical applications and any other type of applications/circuits that require very large on-chip resistors.
As the microphone can be biased at different levels, depending on manufacturer requirements, the input is usually ac-coupled onto the audio chip, so that the rest of the Analog Front End (AFE) can independently set the common-mode at an appropriate level to enable proper operation.
The input decoupling happens through the high pass filter formed by CHPF (101) and RHPF (102). For medical systems, this pole can be of the order of a few Hz, while for microphone signals, the pole can be in the 10 Hz range. Traditionally, this has been achieved easily using an external Printed Circuit Board (PCB) decoupling capacitor on the order of a few μF, and either using an external resistor or integrating on-chip a resistor that is in the range of 10 KΩ, depending on the required precision of the pole location.
In today's Internet Of Things (IoT) era, with the proliferation of the number of channels that need to be processed and the push towards using advanced digital silicon nodes (such as 20 nm and smaller geometries) for maximum feature integration and higher speed in the digital cores and Physical Layers Interfaces, using 2 sets of external capacitors for each channel has become prohibitive to customers, in terms of Build Of Materials (BOM) cost and, more importantly, PCB space, as the form factors of hand-held and wearable devices are ever shrinking. This has led many leading manufacturers to go for integrated solutions that eliminate these external components, while still driving for very low chip costs.
In the next section, the existing solutions to meeting these requirements are explained, while highlighting their limitations.